(1) Technical Field
This invention generally relates to electronic circuits, and more specifically to digital step attenuator circuits.
(2) Background
An attenuator is an electronic device that reduces the power of a signal without appreciably distorting its waveform. Attenuators are usually passive devices made from simple voltage divider networks, and are frequently used to lower voltage, dissipate power, and/or to improve impedance matching. For example, in measuring signals, attenuators are used to lower the amplitude of a signal under test a known amount to enable measurements, or to protect the measuring device from signal levels that might damage it. Attenuators are also used to match impedance by lowering the apparent standing wave ratio (SWR).
Digital step attenuators (DSA's) are frequently used with radio frequency (RF) systems such as transceivers for broadcast radio, cellular telephones, and RF based digital networks (e.g., WiFi, Bluetooth). Typical DSA's consist of a series cascade of switchable (2-state), impedance-matched attenuator stages, whose attenuation values are binary weighted. For example, FIG. 1 is a schematic diagram of a typical prior art binary-weighted DSA 100. Shown are 7 attenuator stages formed of series-connected switchable (2-state) “pi” type attenuators 102 and “bridged-T” type attenuators 104.
In operation, a 7-bit binary code is applied to the control lines C16-C0.25 of the DSA 100 to select any or all of the attenuator stages 102, 104 to attenuate a signal between the input port RFin and the output port RFout, in equal increments (0.25 dB per step in this example). Thus, for the illustrated embodiment, a binary control signal of “0111111” will provide an attenuation (negative gain) of −15.75 dB, while a binary control signal of “1000000” will provide an attenuation of −16 dB. For the purpose of this disclosure, an ON attenuator stage is defined to be in “attenuation mode” to provide a designed attenuation level. Conversely, an OFF attenuator stage is bypassed to provide no attenuation and defined to be in “insertion loss mode”.
FIG. 2 is a schematic diagram of a prior art “pi” switchable attenuator circuit 102. To turn the attenuator circuit 102 ON (attenuation mode), bypass switch 200 is opened and shunt switches 202, 204 are closed, resulting in a conventional “pi” type attenuator configuration. To turn the attenuator circuit 102 OFF (insertion loss mode), bypass switch 200 is closed and shunt switches 202, 204 are opened, effectively bypassing the entire attenuator circuit 102. The attenuation characteristics of a “pi” type attenuator are well known to those skilled in the art.
FIG. 3 is a schematic diagram of a prior art “bridged T” switchable attenuator circuit 104. To turn the attenuator circuit 104 ON (attenuation mode), bypass switch 300 is opened and shunt switch 302 is closed, resulting in a conventional “bridged T” type attenuator configuration. To turn the attenuator circuit 104 OFF (insertion loss mode), bypass switch 300 is closed and shunt switch 302 is opened, effectively bypassing the entire attenuator circuit 104. The attenuation characteristics of a “bridged T” type attenuator are well known to those skilled in the art.
A problem with a binary-weighted DSA 100 using “pi” switchable attenuator stages 102 and “bridged T” switchable attenuator stages 104 is that the component switching elements in the attenuator stages do not turn ON and OFF at the same rate. For field effect transistor (FET's) used as the switching elements, typically the turn on time is faster than the turn off time. This creates a scenario whereby various attenuator stages can temporarily present less attenuation as they are changing states. This asymmetrical switching produces a transient glitch at the DSA output, which can degrade the performance of a feedback communication system in which such a DSA is embedded. For example, to program the example 7-bit DSA 100 from 15.75 dB attenuation to 16 dB attenuation would require toggling all seven of the control bits C16-C0.25 simultaneously as shown in Table 1:
TABLE 1decimal codeC16C8C4C2C1C0.5C0.25Ideal Gain (db)590111111−15.75601000000−16.00
As a result of such asymmetric switching, such binary-weighted DSA's suffer from switching transients (glitches) during some code transitions because various attenuator stages simultaneously toggle with different turn-on/turn-off transient responses. For example, FIG. 4 is a diagram showing a switching glitch generated by a typical example of the prior art circuit shown in FIG. 1, for a worst case state transition. In this example, the measured glitch amplitude 400 in switching from one attenuation value 402 to another attenuation value 404 is larger than about 6 dB. When such a DSA is part of an automatic gain control loop (AGC) used to compensate for variations in received signal strength, such glitches may introduce an unwanted detection error.
Attempts have been made to introduce timing delay elements into binary-weighted DSA's to control the sequencing of the attenuator stage switching elements. However, such approaches eliminate positive glitches, but still suffer from large negative glitches. Furthermore, the introduction of a delay has the drawback that it increases the switching time for the DSA as a whole.
Accordingly, there is a need for a digital step attenuator circuit that reduces the amplitude of switching transients (glitches) during code transitions, and which reduces both positive and negative glitches. The present invention addresses this need.